1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a receiver and a receiving method, and, in particular, to a receiver that uses a digital channel filter capable of controlling a center frequency according to a selected channel, instead of a phase locked loop (PLL) frequency synthesizer having a complicated block configuration and thus a high current consumption, so as to improve the efficiency.
2. Description of the Related Art
Digital Multimedia Broadcasting (DMB) is a digital wireless communication service that provides multimedia content through a microwave band currently used for analog television (TV) broadcasts. In order to provide such a service, a DMB chip should be secured. Therefore, a chip having a small size and low power consumption is required. Digital signal processing research and development has led to a digital channel filter having a high selectivity. Accordingly, a recent trend is to select a low intermediate frequency, perform analog to digital (A/D) conversion of the selected frequency, and digitally filter the converted frequency.
A receiver that does not use the digital channel filter, but uses a PLL frequency synthesizer will now be described with reference to FIGS. 1 and 2. FIG. 1 is a view showing the configuration of a wireless receiver with a PLL frequency synthesizer according to the related art. FIG. 2 is a schematic view showing spectrums of frequency signals output by individual blocks of the wireless receiver of FIG. 1.
First, a tunable band pass filter (BPF) 10 receives a radio frequency (RF) signal received by an antenna and a control signal of a digital demodulator 70 according to channel selection by a main body (not shown) connected to the receiver. The tunable BPF 10 passes a wideband frequency signal including a desired signal. FIG. 2A shows the frequency spectrum of a signal “a” received by the antenna and FIG. 2B shows the frequency spectrum of the signal “b” passed by the tunable BPF 10. The tunable BPF 10 passes a certain spectrum of the signal “a” and outputs a signal having center frequencies of 200 MHz and 208 MHz. An Low Noise Amplifier (LNA) 20 amplifies the output signal on the basis of the control signal of the digital demodulator 70 to obtain an appropriate gain and outputs the amplified signal (signal “c”).
A voltage controlled oscillator (VCO) 80 generates a local oscillation frequency and supplies the local oscillation frequency to a frequency divider 120. The frequency divider 120 transforms the high-frequency signal supplied from the voltage controlled oscillator 80 into a low frequency signal at a certain rate, which may be predetermined, and supplies the low frequency signal to a phase detector 100. The phase detector 100 compares the supplied signal with a reference frequency signal that is supplied as a reference of the PLL frequency synthesizer by a reference frequency oscillator 110, and outputs a signal having a duty cycle corresponding to the difference between the two signals. A loop filter 90 receives the signal output by the phase detector 100, converts the received signal into a DC control signal, and outputs the DC control signal to the voltage controlled oscillator 80. The voltage controlled oscillator 80 generates a local oscillation frequency signal according to the DC control signal. The local oscillation frequency signal is input to the frequency divider 120, as described above. In this way, a closed loop is formed, and the local oscillation frequency is locked to a frequency based on the low frequency reference frequency. Further, the voltage controlled oscillator 80 also transmits an output signal “d” to a mixer 30. The output signal “d” can be generated by selecting one frequency among frequencies of various tones. For example, in FIG. 2D, a signal having a frequency of 195 MHz (or 203 MHz) is output among frequency signals depicted by the dotted lines.
The mixer 30 mixes the signal “d,” output by the voltage control oscillator 80 with the RF signal “c”, as shown in FIG. 2C, amplified by the LNA 20 to perform frequency down-conversion, and outputs an intermediate frequency (IF) signal “e”, as shown in FIG. 2E, having a fixed frequency corresponding to the difference between the frequencies of the two signals. The IF signal “e” is an IF signal having a fixed center frequency of 5 MHz corresponding to the difference between the signal “c” (200 MHz) and the signal “d” (195 MHz). Alternatively, when a signal of 203 MHz instead of the signal of 195 MHz is selected as the signal “d”, an IF signal having a fixed center frequency of 5 MHz corresponding to the difference between 208 MHz of the signal “c” and 203 MHz of the signal “d” may be output. A channel BPF 40 receives the IF signal “e”, and selectively passes only a desired channel. An IF amplifier 50 amplifies the desired channel according to the control signal of the digital demodulator 70. FIGS. 2F and 2G show signals “f” and “g” before and after the IF amplifier 50, respectively. As can be seen from FIGS. 2F and 2G, a signal having a fixed center frequency of 5 MHz is selected and output. The signal “g” is input to an A/D converter 60 and is converted into a digital signal. The digital demodulator 70 receives and demodulates the digital signal, and outputs the demodulated digital signal to a decoder of the main body (not shown).
In the above-described receiver, the PLL frequency synthesizer used for such a receiver occupies a large proportion of the chip layout area, thereby increasing its cost. Further, since the PLL frequency synthesizer needs many blocks, such as a VCO, a loop filter, and a frequency divider, the current consumption increases. As a result, when the PLL frequency synthesizer is used in a portable device, its battery life decreases. Further, since the tunable BPF 10 should simultaneously perform channel selection and image channel removal and selectively operate according to a channel, performance decreases. Also, the manufacturing process is more complicated.